The Cell Broadband Engine processor, jointly developed by Sony, Toshiba, and IBM, combines one Power and eight Single Instruction Multiple Data (SIMD) cores, so-called Synergistic Processing Elements (SPEs), in a “supercomputer-on-a-chip”. Besides its intended use in next-generation game consoles, high-definition television sets, and Cell BE processor-based workstations, the processor is interesting for other application scenarios as well. One promising idea is to exploit Cell BE for function offload, where compute-intensive processing tasks are moved from application systems to specialized offload systems, enabling existing applications to benefit from the computing power of Cell BE.

An especially pressing subject in today’s application environments is the acceleration of XML processing. XML has emerged as the de facto standard for exchanging and handling data and information, but its processing still shows a tremendous lack of performance. In particular, XML parsing, the very basic step of processing XML, increases the load on application systems that are already at their limits.

This paper describes the design, prototype implementation, and evaluation of a system architecture for XML offload to a Cell BE processor-based system, bringing together a new powerful processor technology and an increasingly important software technology that suffers from its performance problem. The presented system architecture consists of two elements: a basic infrastructure and specialized offload services such as an accelerator parser service. The infrastructure provides means to move processing tasks from application systems to designated offload systems, and is made up of three components: a client, a server, and a communication interface. The client transparently integrates into existing Java parser interfaces, namely the Java API for XML Processing (JAXP). The server provides various offload services including XML parser services. Client and server communicate via a flexible event-based communication interface. The main focus of the infrastructure is on transparent integration and flexibility. In order to obtain optimal XML parsing performance, the accelerator parser service must fit well to the Cell BE processor. We choose an approach based on a novel enhanced finite state technology. The resulting parser can be fit into the relatively small, fast local memory of the SPEs.

The evaluation of the infrastructure discloses a surprising bottleneck in existing Java parser interfaces. The major causes of this problem are inherent restrictions of the Java programming language, like the absence of C++-style pointers. The problem presents a serious roadblock for various Java-based offload and acceleration scenarios, even beyond XML parsing. In the paper, we briefly present our findings and some approaches that could solve the problem, but don’t have conclusive results yet. Further work is required. We were, however, able to demonstrate significant performance gains for XML parsing by exploiting the Cell BE processor with a novel approach to parsing technology. In non-Java scenarios, this accelerator can be used to realize high-performance XML offload and accelerator solutions. Currently, our accelerator parser provides over three times the throughput on a Cell BE processor-based system than libxml, one of the fastest existing XML parsers, on a comparable Intel-based computer system. Further work to improve the parser’s performance is in progress.

In contrast to our presentation at the XML 2005 Conference, this paper focuses on the accelerator parser service and goes into detail about its design and implementation.